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V 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74SSTV16857 14-Bit Registered Buffer Product Features PI74 SSTV16857 is designed for low-voltage operation, VDD = VDDQ = 2.3V to 2.7V Supports SSTL_2 Class I and II specifications SSTL_2 Input and Output Levels Designed for DDR Memory Flow-Through Architecture Package available: 48-pin 240 mil wide plastic TSSOP (A) 48-pin 173 mil wide plastic TVSOP (K) Product Description Pericom Semiconductors PI74SSTV16857 series of logic circuits are produced using the Companys advanced 0.35 micron CMOS technology, achieving industry leading speed. The 14-bit PI74SSTV16857 universal bus driver is designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for the RESET input which is LVCMOS. Data flow from D to Q is controlled by the differential clock , CLK, CLK and RESET. Data is triggered on the positive edge of CLK. CLK must be used to maintain noise margins. RESET must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock, are switched off. Pericoms PI74SSTV16857 is characterized for operation from 0 to 70C. Logic Block Diagram CLK CLK RESET D1 38 39 34 48 35 R D CLK 1 Q1 VREF TO 13 OTHER CHANNELS Product Pin Configuration Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK CLK VDD GND VREF RESET D8 D9 D10 D11 D12 VDD GND D13 D14 Product Pin Description Pin Name RESET CLK CLK D Q GND VDD VDDQ VREF Description Reset (Active Low) Clock Input Clock Input Data Input Data Output Ground Core Supply Voltage Output Supply Voltage Input Reference Voltage Inputs RESET L H H CLK X L or H CLK X L or H D X H L X Outputs Q L H L Q o(2) 48-Pin 40 A, K 39 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Truth Table(1) Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 Notes: 1. H = High Signal Level 2. Output level before the L = Low Signal Level indicated steady state = Transition LOW-to-HIGH input conditions were = Transition HIGH-to-LOW established. X = Irrelevant 1 PS8460C 06/04/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74SSTV16857 14-Bit Registered Buffer Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Ite m Storage temperature Supply voltage Input voltage(1) O utput voltage (1,2) Symbol/Conditions Tstg VDD or VDDQ VI VO IIK, VI<0 IOK, VO<0 IO, VO = 0 to VDDQ IDD, IDDQ or IGND JA Ratings 65 to 150 0.5 to 3.6 0.5 to VDD +0.5 0.5 to VDDQ +0.5 50 50 50 100 70 Units C V Input clamp current O utput clamp current Continuous output current VDD, VDDQ or GND current/pin Package Thermal Impedance(3) mA C/W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions Parame te rs VDD VDDQ VREF VTT VIH VIL VIH VIL VIN VID VIX IOH IOL TA Supply Voltage I/O Supply Voltage Reference Voltage VREF = 0.5X VDDQ Termination Voltage DC Input High Voltage DC Input Low Voltage Input High Voltage Input Low Voltage Input Voltage Level Input Differential Voltage RESET Data Inputs De s cription M in. 2.3 2.3 1.15 VREF 0.04 VREF +0.15 0.3 1.7 0.3 0.3 0.36 (VDDQ/2) 0.2 20 20 0 70 C VDDQ +0.6 (VDDQ/2) +0.2 mA Nom. 2.5 2.5 1.25 VREF M ax. 2.7 2.7 1.35 VREF +0.04 VDDQ +0.3 VREF 0.15 VDDQ +0.3 0.8 V Units CLK,CLK Cross Point Voltage of Differential Clock Pair High- Level Output Current Low- Level Output Current Operating Free- Air Temperature 2 PS8460C 06/04/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74SSTV16857 14-Bit Registered Buffer DC Electrical Characteristics Parame te rs VIK VOH (Over the Operating Range, TA = 0C to +70C, VDD = 2.5V 200mV, VDDQ = 2.5V 200mV) Te s t Conditions II = 18mA IOH = 100A IOH = 16mA IOL = 100A IOH =16mA VI = VDD or GND RESET = GND VI = VIH (AC) or VIL (AC), RESET = VDD RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle . RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle VI = VREF 350mV VICR =1.25V, VI(PP) = 360mV VDD 2.3V 2.3V- 2.7V 2.3V 2.3V- 2.7V 2.3V 2.7V M in. Typ.(4) M ax. 1.2 Units VDD 0.2 1.95 0.2 0.35 5 100 TBD mA A/ clock MHz A V VOL II IDD All Inputs Standby (Static) Operating (Static) Dynamic operating - clock only IDDD Dynamic Operating - per each data input TBD IO = 0 2.7V TBD A/ clock MHz/ data Ci Data Inputs CK and CK 2.5V 2.0 2.0 3.5 3.5 pF Notes: 4. Typical values are at VDD = Nominal VDD, TA = +25C. 3 PS8460C 06/04/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74SSTV16857 14-Bit Registered Buffer Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) VDD = 2.5V 0.2V M in. fclock tPD tRST tSL tsu Clock frequency Clock to output time Reset to output time Output slew rate Setup time, fast slew rate(5,7) Setup time, slow slew rate(6,7) Hold time, fast slew rate(5,7) Hold time, slow slew rate(6,7) Data before CK, CK 1 0.75 0.9 0.75 0.9 ns TBD M ax. 170 TBD 5 4 Units MHz ns V/ns th Data after CK, CK Notes: 5. For data signal input slew rate 1V/ns. 6. For data signal input slew rate 0.5V/ns and <1V/ns. 7. CLK, CLK signals input slew rates are 1V/ns. Switching characteristics (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms). Parame te r fmax tpd tphl CLK , CLK RESET Q Q From (Input) To (Output) VDD = 2.5V 0.2V M in. 170 1.1 2.8 5.0 Typ. M ax. Units MHz ns 4 PS8460C 06/04/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74SSTV16857 14-Bit Registered Buffer Test Circuit and Switching Waveforms VTT LVCMOS RESET Input IDD(9) VDD/2 VDD RL = 50 From Output Under Test TEST POINT CL = 30pF(8) tinact 10% tact 0V 90% IDDH IDDL Timing Input Load Circuit Voltage and Current Waveforms Input Active and Inactive Times VICR VICR VI(PP) tw Input VREF VREF VIH Output t PLH VTT t PHL VTT VOH VIL VOL Voltage Waveforms - Pulse Duration Voltage Waveforms - Propagation Delay Times Timing Input tsu VREF LVCMOS VICR VI(PP) RESET Input VIH VDD/2 VIL t PHL VOH VTT VOL th VIH VREF VIL Output Input Voltage Waveforms - Setup and Hold Times Voltage Waveforms - Propagation Delay Times Parameter Measurement Information (VDD = 2.5V 0.2V) Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50. Input slew rate = 1V/ns 20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 350mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF + 350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd. 5 PS8460C 06/04/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74SSTV16857 14-Bit Registered Buffer 48-Pin TSSOP Package (A) 48 .236 .244 6.0 6.2 1 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .0197 BSC 0.50 .007 .010 0.17 0.27 .002 .006 0.05 0.15 48-Pin TSSOP Package (K) 48 .169 .177 4.30 4.50 .0035 .008 0.09 0.20 1 .378 9.60 .386 9.80 .031 .041 0.80 1.05 0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .016 BSC 0.40 .0051 .009 0.13 0.23 .002 .006 0.05 0.15 Max. .047 1.20 Ordering Information Orde ring Code Package Type Orde ring Range 40C to 85C PI74SSTV16857A 48- Pin 240- mil TSSO P PI74SSTV16857K 48- Pin 173- mil TVSO P Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 6 PS8460C 06/04/01 |
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